Field of the Invention
The present invention relates to electronics and, more specifically, to voltage signal development across bit lines during a read operation for memory circuitry such as static random access memory (SRAM) circuitry.
Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
FIG. 1 is a simplified schematic circuit diagram of a portion of a conventional memory array 100 comprising a two-dimensional array of 1-bit SRAM memory cells 102 arranged in rows and columns, of which only one example cell is shown in FIG. 1. As represented in FIG. 1, each cell 102 comprises six transistor devices M1-M6 which are coupled to a word line WL and a pair of bit lines: bit line BL and bit bar line BLb. Each column of the memory array has its own bit line pair BL and BLb, and each row of the memory array has its own word line WL. All of the cells 102 in each column are coupled to the same bit line pair BL and BLb, which are in turn coupled to sense amplifier circuitry (not shown) for that column, and all of the cells 102 in each row are coupled to the same word line WL.
In a “logic 1 high” interpretation, a bit value of 1 is said to be stored in cell 102 if node Q is high and node Qb is low. In that case, devices M1 and M4 will be on, and devices M2 and M3 will be off. On the other hand, a bit value of 0 is said to be stored in cell 102 if node Q is low and node Qb is high. In that case, devices M1 and M4 will be off, and devices M2 and M3 will be on.
The sequence of operations to read the bit value stored in cell 102 is as follows: First, with the word line WL driven low, pre-charge circuitry 104 is turned on (or enabled or coupled, depending on the particular implementation) to pre-charge both the bit line BL and the bit bar line BLb to the same high voltage level. The pre-charge circuitry 104 is then turned off (or disabled or uncoupled, depending on the particular implementation), and, soon after, the word line WL is driven high to turn on devices M5 and M6. Note that the word lines WL of the other rows in the array stay low, such that the other cells 102 in the same column remain isolated from the bit line pair BL and BLb.
If cell 102 stores a bit value of 1, such that Q is high and Qb is low, then, if the word line WL is driven high, the pre-charged bit bar line BLb will be driven towards ground through turned-on devices M5 and M1, while the pre-charged bit line BL will stay high due to turned-on devices M6 and M4. This will result in the development of a positive voltage differential between the bit line BL and bit bar line BLb (i.e., the voltage of BL is greater than the voltage of BLb), which the sense amplifier circuitry will detect as a stored bit value of 1 in cell 102.
On the other hand, if cell 102 stores a bit value of 0, such that Q is low and Qb is high, then, if the word line WL is driven high, the pre-charged bit line BL will be driven towards ground through turned-on devices M6 and M3, while the pre-charged bit bar line BLb will stay high due to turned-on devices M5 and M2. This will result in the development of a negative voltage differential between the bit line BL and bit bar line BLb (i.e., the voltage of BL is less than the voltage of BLb), which the sense amplifier circuitry will detect as a stored bit value of 0 in cell 102.
In general, the faster the development of a voltage difference between bit lines BL and BLb of sufficient magnitude to be detected, the faster will the sense amplifier circuitry be able to read the stored bit value. In some cases, a slow development of a voltage difference between BL and BLb may cause failure of the sense amplifier to read the correct value.
One of the problems with memory arrays like memory array 100 of FIG. 1 is that leakage currents can slow down the speed at which data can be read from the memory array. In particular, leakage currents can draw charge from the pre-charged bit lines BL and/or BLb between the time that the pre-charge circuitry 104 is turned off and the time that the word line is driven high, such that one or both bit lines will be below its desired pre-charged voltage level.
For example, if cell 102 stores a bit value of 1, such that Q is high and Qb is low, leakage current in bit line BL will lower the voltage level of BL from its pre-charged voltage level over time. If the word line WL is eventually driven high, then the voltage level of bit bar line BLb will be driven towards ground (i.e., zero), but because the voltage level of bit line BL was diminished by leakage current, it will take longer for the voltage level of bit bar line BLb to decrease enough to generate a sufficient voltage difference between the bit line pair to enable the sense amplifier circuitry to detect the stored bit value. Moreover, if the leakage current in bit line BL is sufficiently greater than any leakage current in bit bar line Blb, then it is possible that the initial voltage difference between the bit line pair will result in the sense amplifier circuitry detecting the wrong stored bit value (i.e., a 0 instead of a 1 in this example).
To address the issue of leakage currents in bit lines, conventional memory array 100 of FIG. 1 is implemented with leakage abatement circuits (LAC) 106 and 106b, where LAC 106 is configured to inject an appropriate amount of current into bit line BL to compensate for leakage current in that bit line, and LAC 106b is configured to inject a (potentially different) appropriate amount of current into bit bar line BLb to compensate for leakage current in that bit line.